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m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) description the m5m4v16g50dfp is a 2-bank x 262,144-word x 32-bit synchronous gram, with lvttl interface. all inputs and outputs are referenced to the rising edge of clk. the m5m4v16g50dfp can operate at frequencies of 100+ mhz. the block write and write-per-bit functions provide improved performance in graphic memory systems. features - single 3.3v?.3v power supply - clock frequencies of 125 mhz - fully synchronous operation referenced to clock rising edge - dual bank operation controlled by a10(bank address) - internal pipelined operation: column address can be changed every clock cycle - programmable /cas latency ( lvttl: 2 and 3) - programmable burst length (1/2/4/8 and full page) - programmable burst type (sequential / interleave) - byte control using dqm0 - dqm3 signals in both read and write cycles - persistent write-per-bit (wpb) function - 8 column block write (bw) function - auto precharge / all bank precharge controlled by a9 - auto refresh and self refresh capability - 2048 refresh cycles /32ms - lvttl interface - 100 pin qfp package with 0.65mm lead pitch max. frequency clk access time m5m4v16g50dfp - 8 125mhz 7ns m5m4v16g50dfp- 10 100mhz 8ns preliminary some of contents are described for general products and are subject to change without notice. m5m4v16g50dfp- 12 83mhz 10ns
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) clk : master clock cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dsf : special function enable a0-10 : address input a0-9 : row address inputs a0-7 : column address inputs a10 : bank address dq0-31 : data i/o dqm0-3 : output disable/ write mask vdd : power supply vddq : power supply for output vss : ground vssq : ground for output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 a7 a6 a5 a4 vss nc nc nc nc nc nc nc nc nc nc vdd a3 a2 a1 a0 dq29 vssq dq30 dq31 vss nc nc nc nc nc nc nc nc nc nc vdd dq0 dq1 vssq dq2 dq28 vddq dq27 dq26 vssq dq25 dq24 vddq dq15 dq14 vssq dq13 dq12 vddq vss vdd dq11 dq10 vssq dq9 dq8 vddq nc dqm3 dqm1 clk cke dsf nc a9 dq3 vddq dq4 dq5 vssq dq6 dq7 vddq dq16 dq17 vssq dq18 dq19 vddq vdd vss dq20 dq21 vssq dq22 dq23 vddq dqm0 dqm2 /we /cas /ras /cs a10 a8 100 pin qfp 14.0 x 20.0 mm2 0.65 mm pitch
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) block diagram address buffer a0-9 a10 control signal buffer /cs /ras /cas /we dsf clk cke clock buffer memory array bank #0 memory array bank #1 control circuitry i/o buffer dq0-31 mode register dqm0-3 type designation code m 5m 4 v 16 g 5 0 d fp - 8 cycle time (min.) 8: 8ns, 10: 10ns, 12: 12ns package type fp: qfp process generation function 0: random column, 1: 2n-rule organization 2 n 5: x32 synchronous graphics ram density 16:16m bits interface v:lvttl memory style (dram) use, recommended operating conditions, etc mitsubishi main designation this rule is applied only to synchronous dram family. mask register color register
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) pin function clk input master clock: all other inputs are referenced to the rising edge of clk. cke input clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is stopped. cke is also used to select auto / self refresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, / we, and dsf input combination of /ras, /cas, /we, and dsf defines basic commands. a0-9 input a0-9 specify the row / column address in conjunction with ba. the row address is specified by a0-9. the column address is specified by a0-7. a9 is also used to indicate precharge option. when a9 is high at a read / write command, an auto precharge is performed. when a9 is high at a precharge command, both banks are precharged. a10 input bank address: a10 (ba) specifies the bank to which a command is applied. a10 (ba) must be set with act, pre, read, write commands. dq0-31 input / output data in/data out are referenced to the rising edge of clk. these pins are used for input mask pins for write-per-bit and column/byte mask inputs for block writes. dqm0 - dqm3 input input/output byte mask: when dqm0-3 are high during a write, data for the current cycle is masked. when dqm0-3 are high during a read, output data is disabled at the next cycle. dqm0 controls byte 0 (dq7-0), dqm1 controls byte 1 (dq15-8), dqm2 controls byte 2 (dq23-16), and dqm3 controls byte 3 (dq31-24). vref input reference voltage for all inputs. vdd, vss power supply power supply for the memory array and peripheral circuitry. vddq, vssq power supply vddq and vssq are supplied to the output buffers only.
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) basic functions the m5m4v16g50dfp provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas, /we, and dsf at clk rising edge. in addition to 3 signals, /cs ,cke and a9 are used as chip select, refresh option, and precharge option, respectively. for a more detailed definition of commands, please see the command truth table. activate (act) [/cs, /ras, dsf = l, /cas, /we = h] act command activates a row in an idle bank indicated by a10 (ba) and row address selected by a0 - a9. activate with wpb enable (actwpb) [/cs, /ras = l, /cas, /we, dsf = h] this command is the same as activate except that write-per-bit (wpb) is enabled. the mask register? contents are used as the wpb data. read (read) [/cs, /cas, dsf = l, /ras, /we = h] read command starts burst read from the active bank indicated by a10 (ba). first output data appears after /cas latency. when a9 = h at this command, the bank is deactivated after the burst read (auto-precharge, reada ). write (write) [/cs, /cas, /we, dsf = l, /ras = h] write command starts burst write to the active bank indicated by a10 (ba). total data length to be written is set by burst length. when a9 = h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/cs, /ras, /we, dsf = l, /cas = h] pre command deactivates the active bank indicated by a10 (ba). this command also terminates burst read /write operation. when a9 = h at this command, both banks are deactivated (precharge all, prea ). /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a9 precharge option @precharge or read/write command clk define basic commands dsf command
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) auto-refresh (refa) [/cs, /ras, /cas, dsf = l, /we, cke = h] refa command starts auto-refresh cycle. refresh address including bank address are generated inter- nally. after this command, the banks are precharged automatically. both banks must be precharged before this command can begin. self-refresh (refs) [/cs, /ras, /cas, dsf, cke = l, /we = h] refs command starts self-refresh cycle. the self-refresh cycle will continue while cke remains low. when cke goes high, self-refresh is exited. refresh address including bank address are generated inter- nally. after this command, the banks are precharged automatically. both banks must be precharged before this command can begin. burst terminate (term) [/cs, /we, dsf = l, /ras, /cas = h] term command stops the current burst operation. during read cycles, burst data stops after cas latency is met. no operation (nop) [/cs, dsf = l, /ras, /cas, /we = h] nop command does not perform any operation on the sgram. mode register set (mrs) [/cs, /we, /ras, /cas, dsf = l] mrs command loads the mode register that defines how the device operates. the address pins, a0 - a10, are used as input pins for the mode register data. this command must be issued after power-on to initialize the sgram. the mode register can only be set when both banks are idle. during the two cycles following this command, the sgram cannot accept any other commands. special register set (srs) [/cs, /we, /ras, /cas = l, dsf = h] srs command sets the color and mask registers. during the two cycles following this command, the sgram cannot accept any other commands. masked block write (bw) [/cs, /cas, /we = l, /ras, dsf = h] bw command starts the 8 column block write function. burst length = 1 is assumed. write data comes from the color register and column address mask data is applied on the dqs. when a9 = h at this command, the bank is deactivated after the burst write (auto-precharge, bwa ). basic functions (continued)
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) command truth table h=high level, l=low level, ba=bank address, col.=column address (a0-a7) row add.=row address (a0-a9), x=don't care, n=clk cycle number command mnemonic cke n-1 cke n /cs /ras /cas /we a10 a9 a0-8 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h x l l h h ba row add. single bank precharge pre h x l l h l ba l x precharge all banks prea h x l l h l x h x column address entry & write write h x l h l l ba l col. column address entry & write with auto- precharge writea h x l h l l ba h col. column address entry & read read h x l h l h ba l col. column address entry & read with auto- precharge reada h x l h l h ba h col. auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate term h x l h h l x x x mode register set mrs h x l l l l opcode dsf x l l l l l l l l l l x l l l special register set srs h x l l l l h row address entry & bank activate actwpb h x l l h h ba row add. h column address entry & masked block write bw h x l h l l ba l col. masked block write with auto-precharge bwa h x l h l l ba h col. h h opcode
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) function truth table current state /cs /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l x term illegal*2 l h l h ba, ca, a9 read / reada illegal*2 l l h h ba, ra act bank active; latch ra; no mask l l l h x undefined illegal l l l h x refa auto-refresh*5 l l l l op-code, mode-add srs special register set*5 row active h x x x x desel nop l h h h x nop nop l h h l ba term nop l h l h ba, ca, a9 read / reada begin read; latch ca; determine auto-precharge l h l l ba, ca, a9 write / writea begin write; latch ca; determine auto-precharge l l h h ba, ra act bank active / illegal*2 l l h l ba, a9 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode-add srs special registeset *5 dsf x l l l l h l h x l l l l l l l h l h h l x undefined illegal h l h l h x undefined illegal h l h l l ba, ca, a9 write / writea illegal*2 l l h l l ba, ca, a9 bw / bwa illegal*2 h l l h h ba, ra actwpb bank active; latch ra; use mask h l l h l x undefined illegal h l l h l ba, a9 pre / prea nop*4 l l l l l op-code, mode-add mrs mode register set*5 l l l l l op-code, mode-add mrs illegal l l l h h ba, ra actwpb bank active / illegal*2 h l h l l ba, ca, a9 bw / bwa block write; latch ca; determine auto-precharge h
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) function truth table (continued) current state /cs /ras /cas /we address command action read h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a9 read / reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a9 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a9 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add srs illegal dsf x l l l l l l l h l h l l ba, ca, a9 bw / bwa terminate burst, latch ca, block write, determine auto- precharge*3 h l l h h ba, ra actwpb bank active / illegal*2 l l l l l op-code, mode-add mrs illegal l write h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a9 read / reada terminate burst, latch ca, begin read, determine auto- precharge*3 l h l l ba, ca, a89 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a9 pre / prea terminate burst, precharge l l l h x refa illegal l l l l srs illegal x l l l l l l l h op-code, mode-add l l l l mrs illegal l op-code, mode-add l h l l ba, ca, a9 bw / bwa terminate burst, latch ca, block write, determine auto- precharge*3 l l l h h ba, ra actwpb bank active / illegal*2 l
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) function truth table (continued) current state /cs /ras /cas /we address command action read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a9 read / reada illegal l h l l ba, ca, a9 write / writea illegal l l h h ba, ra actwpb bank active / illegal*2 l l h l ba, a9 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add srs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a9 read / reada illegal l h l l ba, ca, a9 write / writea illegal l l h h ba, ra actwpb bank active / illegal*2 l l h l ba, a9 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add srs illegal dsf x l l l l h l l h x l l l l h l l h l h l l ba, ca, a9 bw / bwa illegal h l l h h ba, ra act bank active / illegal*2 l l l l l op-code, mode-add mrs illegal l l l l l op-code, mode-add mrs illegal l l h l l ba, ca, a9 bw / bwa illegal h l l h h ba, ra act bank active / illegal*2 l
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) function truth table (continued) current state /cs /ras /cas /we address command action pre - charging h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba term illegal*2 l h l h ba, ca, a9 read / reada illegal*2 l l h h ba, ra actwpb illegal*2 l l h l ba, a9 pre / prea nop*4 (idle after trp) l l l h x refa illegal l l l l op-code, mode-add srs illegal row activating h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba term illegal*2 l h l h ba, ca, a9 read / reada illegal*2 l l h h ba, ra actwpb illegal*2 l l h l ba, a9 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add srs illegal dsf x l l l l l l h x l l l h l l h l h l l ba, ca, a9 write / writea illegal*2 l l h l l ba, ca, a9 bw / bwa illegal*2 h l l h h ba, ra act illegal*2 l l l l l op-code, mode-add mrs illegal l l h l l ba, ca, a9 write / writea illegal*2 l l h l l ba, ca, a9 bw / bwa illegal*2 h l l l l op-code, mode-add mrs illegal l l l h h ba, ra act illegal*2 l
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) function truth table (continued) current state /cs /ras /cas /we address command action write re- covering h x x x x desel nop l h h h x nop nop l h h l ba term illegal*2 l h l h ba, ca, a9 read / reada illegal*2 l l h h ba, ra actwpb illegal*2 l l h l ba, a9 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add srs illegal dsf x l l l h l l h l l l l op-code, mode-add mrs illegal l l h l l ba, ca, a9 write / writea illegal*2 l l h l l ba, ca, a9 bw / bwa illegal*2 h l l h h ba, ra act illegal*2 l re- freshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l h ba, ca, a9 read / reada illegal l l h h ba, ra act illegal l l h l ba, a9 pre / prea illegal l l l h x refa illegal l l l l srs illegal x l l l l l l h op-code, mode-add l l l l mrs illegal l op-code, mode-add l h l l ba, ca, a9 write / writea illegal l l h l l ba, ca, a9 bw / bwa illegal h l l h h ba, ra act illegal l
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) function truth table (continued) abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed. current state /cs /ras /cas /we address command action mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l ba term illegal l h l h ba, ca, a9 read / reada illegal l l h h ba, ra actwpb illegal l l h l ba, a9 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add srs illegal dsf x l l l h l l h l l l l op-code, mode-add mrs illegal l l l h h ba, ra act illegal l l h l l ba, ca, a9 write / writea illegal l l h l l ba, ca, a9 bw / bwa illegal h
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command. current state cke n-1 cke n /cs /ras /cas /we add action self- refresh*1 h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain self-refresh) all banks idle*2 h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle*3 l h x x x x x exit clk suspend at next cycle*3 l l x x x x x maintain clk suspend dsf x x x x x x x x x x x l x x x x x x x x x x
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sgram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqm0-3 high and nop condition at the inputs. 2. maintain stable power, stable clock, and nop input conditions for a minimum of 500?. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sgram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when both banks are in idle state. after trsc from a mrs command, the sgram is ready for new command. 0 1 burst type sequential interleaved cl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 cas latency operating mode 0 0 - burst read and single write all others are reserved normal operation a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ltmode bt bl 0 bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 bt= 0 bt= 1 1 2 4 8 4 8 /cs /ras /cas /we a10, a9 -a0 clk v a10 0 0 0 a7 0 0 - a8 0 1 - a9 0 0 - a10 lvttl reserved reserved reserved reserved reserved reserved 2 3 dsf burst length reserved reserved full page reserved reserved reserved reserved reserved reserved reserved
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) special register the mask register and color register can be loaded by setting the special register (srs). if cr and mr are both high, data in the mask and color registers will be unknown.after trsc from a srs command, the sgram is ready for new command. 0 1 mask register no load operation load mask a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 /cs /ras /cas /we a10, a9 -a0 clk v a10 0 0 0 dsf cr mr 0 0 0 0 0 mr operation 0 1 color register no load operation load color cr operation
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) command address clk read y q0 q1 q2 q3 write y d0 d1 d2 d3 /cas latency burst length burst length dq burst type cl= 3 bl= 4 a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 note: full page burst is an extension of the above tables of sequential addressing with the length being 256.
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) operational description bank activate the sgram has two independent banks. each bank is activated by the act command with the bank address (a10/ba). a row is indicated by the row address a9-0. the minimum activation interval between one bank and the other bank is trrd. precharge the pre command deactivates the bank indicated by a10/ba. when both banks are active, the precharge all command (prea, pre + a9=h) is available to deactivate them at the same time. after trp from the precharge, an act command can be issued. read after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl -1) consecutive data when the burst length is bl. the start address is specified by a7-0, and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data (in case of bl=4) by interleaving the dual banks. when a9 is high at a read command, the auto-precharge (reada) is performed. any command (read, write, pre, act) to the same bank is inhibited until the internal precharge is complete. the internal precharge start timing depends on /cas latency. the next act command can be issued after trp from the internal precharge timing. bank activation and precharge all (bl=4, cl=3) clk command a0-8 a9 a10 dq act xa xa 0 read y 0 0 qa0 qa1 qa2 qa3 act xb xb 1 pre trrd trcd 1 act xb xb 1 precharge all tras trp
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) read with auto-precharge (bl=4, cl=3) clk command a0-8 a9 a10 dq act xa xa 0 read y 1 0 qa0 qa1 qa2 qa3 act xa xa 0 internal precharge begins trcd trp dual bank interleaving read (bl=4, cl=3) clk command a0-8 a9 a10 dq act xa xa 0 read y 0 0 read y 0 1 qa0 qa1 qa2 qa3 qb0 qb1 qb2 act xb xb 1 pre 0 0 trcd /cas latency burst length read auto-precharge timing (bl=4) clk command act read internal precharge start timing dq qa0 qa1 qa2 qa3 dq qa0 qa1 qa2 qa3 cl=3 cl=2
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) write after trcd from the bank activation, a write command can be issued. 1st input data is set in the same cycle as the write. the following (bl -1) data is written into the ram, when the burst length is bl. the start address is specified by a7-0, and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data (in case of bl=4) by interleaving the dual banks. when a9 is high at a write command, the auto-precharge (writea) is performed. any command (read, write, pre, act) to the same bank is inhibited until the internal precharge is complete. the internal precharge begins at twr after the last input datacycle. the next act command can be issued after trp from the internal precharge timing. dual bank interleaving write (bl=4) clk command a0-8 a9 a10 dq act xa xa 0 write y 0 0 write y 0 1 da0 da1 da2 da3 act xb xb 1 pre 0 0 trcd burst length db0 db1 db2 db3 trcd twr write with auto-precharge (bl=4) clk command a0-8 a9 a10 dq act xa xa 0 write y 1 0 da0 da1 da2 da3 act xa xa 0 internal precharge begins trcd trp twr
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) burst interruption [ read interrupted by read ] burst read operation can be interrupted by new read of the same or the other bank. m5m4v16g50dfp allows random column access. read to read interval is minimum 1 clk. [ read interrupted by write ] burst read operation can be interrupted by write of the same or the other bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqm0 - 3 to prevent bus contention. the output is disabled automatically 2 cycles after write assertion. read interrupted by read (bl=4, cl=3) clk command a0-8 a9 a10 dq read yi 0 0 read yk 0 1 qai0 qaj1 qbk0 qbk1 read yj 0 0 qaj0 qbk2 qal0 read yl 0 0 qal1 qal2 qal3 read interrupted by write (bl=4, cl=3) clk command a0-8 a9 a10 q read yi 0 0 qai0 write yj 0 0 d daj0 daj1 daj2 daj3 dqm0-3 dqm0-3 control write control
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) [ read interrupted by precharge ] burst read operation can be interrupted by precharge of the same bank. read to pre interval is mini- mum 1 clk. a pre command disables the data output depending on the /cas latency. the figure below shows examples of when the dataout is terminated. read interrupted by precharge (bl=4) clk command dq read pre q0 q1 q2 q3 cl=3 command dq read pre q0 q1 q2 command dq read pre q0 command dq read pre q0 q1 q2 q3 cl=2 command dq read pre q0 q1 q2 command dq read pre q0
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) [ read interrupted by burst terminate ] similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. read to term interval is minimum 1 clk. the figure below shows examples when the dataout is terminated. read interrupted by burst terminate (bl=4) clk command dq read term q0 q1 q2 q3 cl=3 command dq read term q0 q1 q2 command dq read term q0 command dq read term q0 q1 q2 q3 cl=2 command dq read term q0 q1 q2 command dq read term q0
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) [ write interrupted by write ] burst write operation can be interrupted by new write of the same or the other bank. random column access is allowed. write to write interval is minimum 1 clk. [ write interrupted by read ] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. write to read interval is minimum 1 clk. the input data on dq at the interrupting read cycle is ?on? care? write interrupted by write (bl=4) clk command a0-8 a9 a10 dq write yi 0 0 write yk 0 1 dai0 daj0 daj1 dbk0 write yj 0 0 dbk1 dbk2 write yl 0 0 dal0 dal1 dal2 dal3 write interrupted by read (bl=4, cl=3) clk command a0-8 a9 a10 dq write yi 0 0 qaj0 read yj 0 0 qaj1 dai0 dak0 dak1 dqm0-3 write yk 0 0 read yl 0 1 qbl0
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) [ write interrupted by precharge ] burst write operation can be interrupted by precharge of the same bank. random column access is al- lowed. [ write interrupted by burst terminate ] burst terminate command can terminate burst write operation. in this case, the write recovery time is not required and the bank remains active. the figure below shows the case that 3 words of data are written. random column access is allowed. write to term interval is minimum 1 clk. write interrupted by precharge (bl=4) clk command a0-8 a89 a10 dq write yi 0 0 pre 0 0 dai0 dai1 dqm0-3 act xb xb 0 twr trp write interrupted by burst terminate (bl=4) clk command a0-8 a9 a10 dq write yi 0 0 term dai0 dai1 dqm0-3 dai2
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) auto refresh single cycle of auto-refresh is initiated with refa (/cs= /ras= /cas= dsf= l, /we= /cke= h) command. the refresh address is generated internally. 2048 refa cycles within 32ms refresh 16mbit memory cells. the auto-refresh is performed on each bank alternately (ping-pong refresh). before performing an auto-refresh, both banks must be in the idle state. additional commands must not be supplied to the device before trc from the refa command. auto-refresh clk /cs /ras /cas /we cke a0-9 a10 auto refresh on bank 0 auto refresh on bank 1 minimum trc nop or deslect dsf
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) self refresh self-refresh mode is entered by issuing a refs command (/cs= /ras= /cas= dsf= l, /we= h, cke= l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self- refresh mode, cke is asynchronous and the only enabled input (but asynchronous), all other inputs including clk are disabled and ignored, and power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke (refsx). after trc from refsx both banks are in the idle state and a new command can be issued after trc, but desel or nop commands must be asserted until then. self-refresh clk /cs /ras /cas /we cke a0-9 a10 self refresh entry self refresh exit x 0 minimum trc for recovery stable clk nop new command dsf
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) clk suspend cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self-refresh mode. clk suspend can be per- formed either when the banks are active or idle, but a command at the following cycle is ignored. ext.clk cke int.clk power down by cke clk command pre cke command cke act nop nop nop nop nop nop nop nop nop nop nop nop standby power down active power down nop nop dq suspend by cke clk command dq write d0 d1 d2 d3 cke read q0 q1 q2 q3
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) dqm0 - 3 control dqm0 - 3 is a dual function signal defined as the data mask for writes and the output disable for reads. during writes, dqm0 - 3 masks input data. dqm0 - 3 to write mask latency is 0. during reads, dqm0 - 3 forces output to hi-z. dqm0 - 3 to output hi-z latency is 2. dqm0 masks dq0-7, dqm1 masks dq8-15, dqm2 masks dq16-23, dqm3 masks dq24-031. dqm0 - 3 function clk command dq(0-7) write d0 d2 d3 dqm0 read q0 q1 q3 masked by dqm0=high disabled by dqm0=high dq(8-15) d0 d1 d3 dqm1 q0 q2 q3 masked by dqm1=high disabled by dqm1=high dq(16-23) d0 d2 d3 dqm2 q0 q1 q3 masked by dqm2=high disabled by dqm2=high dq(24-31) d0 d1 d3 dqm3 q1 q2 q3 masked by dqm3=high disabled by dqm3=high d1 d2
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) absolute maximum ratings recommended operating conditions (ta=0 ~ 70?, unless otherwise noted) capacitance (ta=0 ~ 70?, vdd = vddq = 3.3 ?0.3v, vss = vssq = 0v, unless otherwise noted) notes: 1. vih (max) = 5.5v for pulse width less than 10ns. 2. vil (min) = -1.0v for pulse width less than 10ns. symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 ~ 4.6 v vddq supply voltage for output with respect to vssq -0.5 ~ 4.6 v vi input voltage with respect to vss -0.5 ~ 4.6 v vo output voltage with respect to vssq -0.5 ~ 4.6 v io output current 50 ma pd power dissipation ta = 25 ? 1000 mw topr operating temperature 0 ~ 70 ? tstg storage temperature -65 ~ 150 ? symbol parameter limits unit min. typ. max. vdd supply voltage 3.0 3.3 3.6 v vss supply voltage 0 0 0 v vddq supply voltage for output 3.0 3.3 3.6 v vssq supply voltage for output 0 0 0 v vih*1 high-level input voltage all inputs 2.0 vddq+0.3 v vil*2 low-level input voltage all inputs -0.3 0.8 v symbol parameter test condition limits (max.) unit ci(a) input capacitance, address pin 5 pf ci(c) input capacitance, control pin vi=vss f=1mhz vi=25mvrms 5 pf ci(k) input capacitance, clk pin 5 pf ci/o input capacitance, i/o pin 7 pf
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) average supply current from vdd (ta=0 ~ 70?, vdd = vddq = 3.3 ?0.3v, vss = vssq = 0v, unless otherwise noted) ac operating conditions and characteristics (ta=0 ~ 70?, vdd = vddq = 3.3 ?0.3v, vss = vssq = 0v, unless otherwise noted) notes: 1. icc (max) is specified at the output open condition. i i symbol parameter test conditions limits unit min. max. voh (dc) high-level output voltage (dc) ioh=-2ma 2.4 v vol (dc) low-level output voltage (dc) iol= 2ma 0.4 v ioz off-state output current q floating vo=0 ~ vddq -10 10 ? input current vih = 0 ~ vddq+0.3v -10 10 ? symbol parameter test conditions limits(max) unit -8 -10 icc1s*1 operating current, single bank trc=min, tclk=min, bl=1, cl=3 ma icc1d*1 operating current, dual bank trc=min, tclk=min, bl=1, cl=3 ma icc2h standby current, cke=h both banks idle, tclk=min, cke=h ma icc2l standby current, cke=l both banks idle, tclk=min, cke=l ma icc3 active standby current both banks active, tclk=min, cke=h ma icc4*1 burst current tclk=min, bl=4, cl=3, 1 bank idle ma icc5 auto-refresh current trc=min, tclk=min ma icc6 self-refresh current cke <0.2v ma -12 tbd tbd tbd tbd tbd tbd tbd tbd icc7 operating current, block write tclk=min ma tbd
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) ac timing requirements (ta=0 ~ 70?, vdd = vddq = 3.3 ?0.3v, vss = vssq = 0v, unless otherwise noted) input pulse levels : 0.8v to 2.0v input timing measurement level : 1.4v symbol parameter limits -8 -10 min. max. min. max. tclk clk cycle time cl=2 12 15 cl=3 8 10 tch clk high pulse width 3 3.5 tcl clk low pulse width 3 3.5 tt transition time of clk 1 10 1 10 tis 2.5 2.5 tih 1 1 trc row cycle time 96 100 trcd row to column delay 24 30 tras row active time 70 10000 70 10000 trp row precharge time 30 30 twr write recovery time 8 10 trrd act to act delay time 30 30 trsc mode register set cycle time 16 20 tpde power down exit time 8 12 tref refresh interval time 32 32 clk signal 1.4v 1.4v any ac timing is referenced to the input signal crossing through 1.4v. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms -12 min. max. 18 12 4 4 1 10 3 1.5 120 36 84 10000 36 12 36 24 15 32 tbwc block write cycle time 16 20 ns 24 tbpl 8 10 ns 12 input setup time (all inputs) input hold time (all inputs) block write to precharge
m5m4v16g50dfp -8, -10, -12 jan'97 preliminary mitsubishi lsis 16m (2-bank x 262144-word x 32-bit) synchronous graphics ram mitsubishi electric sgram (rev. 0.0) switching characteristics (ta=0 ~ 70?, vdd = vddq = 3.3 ?0.3v, vss = vssq = 0v, unless otherwise noted) output load condition symbol parameter limits unit -8 -10 min. max. min. max. tac access time from clk cl=2 9 11 ns cl=3 7 8 ns toh output hold time from clk 3 3 ns tolz delay time, output low impedance from clk 0 0 ns tohz delay time, output high impedance from clk 3 7 3 8 ns v out v ref =1.4v 50pf 50* v tt =1.4v dq clk output timing measurement reference point 1.4v 1.4v 1.4v 1.4v dq clk tac toh tohz -12 min. max. 14 10 3 0 3 8

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